OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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6.7.1.5 AINTC Memory Map
Table 6-5. AINTC Memory Map
BYTE ADDRESS
0xFFFE E000
REGISTER NAME
DESCRIPTION
Revision Register
REV
0xFFFE E004
CR
Control Register
0xFFFE E008 - 0xFFFE E00F
0xFFFE E010
-
Reserved
GER
Global Enable Register
0xFFFE E014 - 0xFFFE E01B
0xFFFE E01C
-
Reserved
GNLR
Global Nesting Level Register
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E020
SISR
0xFFFE E024
SICR
0xFFFE E028
EISR
0xFFFE E02C
EICR
0xFFFE E030
-
0xFFFE E034
HIEISR
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E038
HIDISR
0xFFFE E03C - 0xFFFE E04F
0xFFFE E050
-
VBR
Vector Base Register
0xFFFE E054
VSR
Vector Size Register
0xFFFE E058
VNR
Vector Null Register
0xFFFE E05C - 0xFFFE E07F
0xFFFE E080
-
Reserved
GPIR
Global Prioritized Index Register
Global Prioritized Vector Register
Reserved
0xFFFE E084
GPVR
0xFFFE E088 - 0xFFFE E1FF
0xFFFE E200 - 0xFFFE E20F
0xFFFE E210- 0xFFFE E27F
0xFFFE E280 - 0xFFFE E28B
0xFFFE E28C - 0xFFFE E2FF
0xFFFE E300 - 0xFFFE E30F
0xFFFE E310 - 0xFFFE E37F
0xFFFE E380 - 0xFFFE E38B
0xFFFE E38C - 0xFFFE E3FF
0xFFFE E400 - 0xFFFE E45B
0xFFFE E45C - 0xFFFE E8FF
0xFFFE E800 - 0xFFFE E81F
0xFFFE E820 - 0xFFFE E8FF
0xFFFE E900 - 0xFFFE E904
0xFFFE E908 - 0xFFFE EEFF
0xFFFE EF00 - 0xFFFE EF04
0xFFFE EF08 - 0xFFFE F0FF
0xFFFE F100 - 0xFFFE F104
0xFFFE F108 - 0xFFFE F4FF
0xFFFE F500
-
SRSR[0] - SRSR[3]
System Interrupt Status Raw / Set Registers
Reserved
-
SECR[0] - SECR[3]
System Interrupt Status Enabled / Clear Registers
-
Reserved
System Interrupt Enable Set Registers
Reserved
ESR[0] - ESR[3]
-
ECR[0] - ECR[3]
System Interrupt Enable Clear Registers
Reserved
-
CMR[0] - CMR[31]
Channel Map Registers (Byte Wide Registers)
Reserved
-
-
Reserved
-
Reserved
HIPIR[0] - HIPIR[1]
Host Interrupt Prioritized Index Registers
Reserved
-
DSR[0] - DSR[1]
Debug Select Registers
Reserved
-
HINLR[0] - HINLR[1]
Host Interrupt Nesting Level Registers
Reserved
-
HIER[0]
Host Interrupt Enable Register
Reserved
0xFFFE F504 - 0xFFFE F5FF
0xFFFE F600
-
HIPVR[0] - HIPVR[1]
-
Host Interrupt Prioritized Vector Registers
Reserved
0xFFFE F608 - 0xFFFE FFFF
90
Peripheral Information and Electrical Specifications
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