OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-4. AINTC System Interrupt Assignments
System Interrupt
Interrupt Name
COMMTX
Source
0
ARM
1
COMMRX
ARM
2
NINT
ARM
3
-
Reserved
4
-
Reserved
5
-
Reserved
6
-
Reserved
7
-
Reserved
8
-
Reserved
9
-
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
-
Reserved
EDMA3_CC0_CCINT
EDMA3_CC0_CCERRINT
EDMA3_TC0_TCERRINT
EMIFA_INT
EDMA CC Region 0
EDMA CC
EDMA TC0
EMIFA
IIC0_INT
I2C0
MMCSD_INT0
MMCSD_INT1
PSC0_ALLINT
RTC_IRQS[1:0]
SPI0_INT
MMCSD
MMCSD
PSC0
RTC
SPI0
T64P0_TINT12
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
-
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
Reserved
PROTERR
SYSCFG Protection Shared Interrupt
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
EDMA TC1
SYSCFG_CHIPINT0
SYSCFG_CHIPINT1
SYSCFG_CHIPINT2
SYSCFG_CHIPINT3
EDMA3_TC1_TCERRINT
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
EMIF_MEMERR
GPIO_B0INT
GPIO_B1INT
GPIO_B2INT
GPIO_B3INT
GPIO_B4INT
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
EMIFB
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
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