OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-103. Module States (continued)
Module State
Module Reset
Module Clock
Module State Definition
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
6.34 Emulation Logic
This section describes the steps to use a third party debugger on the ARM926EJ-S within the
OMAP-L137. The debug capabilities and features for DSP and ARM are as shown below.
DSP:
•
•
•
Basic Debug
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Execution Control
System Visibility
Real-Time Debug
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–
Interrupts serviced while halted
Low/non-intrusive system visibility while running
Advanced Debug
–
–
–
–
Global Start
Global Stop
Specify targeted memory level(s) during memory accesses
HSRTDX (High Speed Real Time Data eXchange)
•
•
Advanced System Control
–
–
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Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
Security
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–
–
–
Configurable levels of security and debug visibility
Halting on a security violation
Debug halts prevented during secure code execution
Memory accesses prevented to secure memory
•
•
Analysis Actions
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–
–
–
–
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Stop program execution
Generate debug interrupt
Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
Analysis Events
–
–
–
–
–
Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
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Peripheral Information and Electrical Specifications
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