OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Analysis Configuration
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Application access
Debugger access
Table 6-105. DSP Debug Features
Category
Hardware Feature
Availability
Unlimited
Software breakpoint
Up to 10 HWBPs, including:
4 precise HWBPs inside DSP core and one of them is
associated with a counter.
Basic Debug
Hardware breakpoint
2 imprecise HWBPs from AET.
4 imprecise HWBPs from AET which are shared for
watch point.
Up to 4 watch points, which are shared with HWBPs,
and can also be used as 2 watch points with data (32
bits)
Watch point
Watch point with Data
Counters/timers
Up to 2, Which can also be used as 4 watch points.
Analysis
1x64-bits (cycle only) + 2x32-bits (water marke counters)
External Event Trigger In
External Event Trigger Out
2
2
ARM:
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Basic Debug
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Execution Control
System Visibility
Advanced Debug
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Global Start
Global Stop
Advanced System Control
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Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
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Security
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Halting on a security violation (by cross-triggering via INTC)
Memory accesses prevented to secure memory (this is ensured by system level security
mechanism)
Program Trace
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Program flow corruption
Code coverage
Path coverage
Thread/interrupt synchronization problems
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Data Trace
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Memory corruption
Timing Trace
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Profiling
Analysis Actions
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Stop program execution
Control trace streams
Generate debug interrupt
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Peripheral Information and Electrical Specifications
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