OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
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Analysis Events
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Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
Analysis Configuration
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Application access
Debugger access
Table 6-106. ARM Debug Features
Category
Hardware Feature
Availability
Unlimited
Software breakpoint
Up to 14 HWBPs, including:
2 precise HWBP inside ARM core which are shared with
watch points.
Basic Debug
Hardware breakpoint
8 imprecise HWBPs from ETM’s address comparators,
which are shared with trace function, and can be used
as watch point too.
4 imprecise HWBPs from ICECrusher.
Up to 6 watch points, including:
2 from ARM core which is shared with HWBPs and can
be associated with a data.
Watch point
8 from ETM’s address comparators, which are shared
with trace function, and HWBPs.
2 from ARM core which is shared with HWBPs.
Analysis
8 watch points from ETM can be associated with a data
comparator, and ETM of Primus has total 4 data
comparators.
Watch point with Data
Counters/timers
3x32-bit (1 cycle ; 2 event)
External Event Trigger In
External Event Trigger Out
Address range for trace
2
2
4
Data qualification for trace
System events for trace control
Counters/Timers for trace control
State Machines/Sequencers
Context/Thread ID Comparator
Independent trigger control units
Capture depth PC
2
20
Trace Control
2x16-bit
1x3-State State Machine
1
12
Primus has 4k bytes ETB
Primus has 4k bytes ETB
Y
On-chip Trace
Capture
Capture depth PC + Timing
Application accessible
6.34.1 JTAG Port Description
The OMAP-L137 target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK,
TMS, TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and
EMU0.
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Peripheral Information and Electrical Specifications
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