OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
6.15.2 McASP Electrical Data/Timing
6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-42 and Table 6-43 assume testing over recommended operating conditions (see Figure 6-33 and
Figure 6-34).
Table 6-42. McASP0 Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Cycle time, AHCLKR0 external, AHCLKR0 input
Cycle time, AHCLKX0 external, AHCLKX0 input
Pulse duration, AHCLKR0 external, AHCLKR0 input
Pulse duration, AHCLKX0 external, AHCLKX0 input
Cycle time, ACLKR0 external, ACLKR0 input
20
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
20
10
2
3
4
ns
ns
ns
10
greater of 2P or 20
Cycle time, ACLKX0 external, ACLKX0 input
greater of 2P or 20
Pulse duration, ACLKR0 external, ACLKR0 input
Pulse duration, ACLKX0 external, ACLKX0 input
Setup time, AFSR0 input to ACLKR0 internal(3)
Setup time, AFSR0 input to ACLKX0 internal(4)
Setup time, AFSX0 input to ACLKX0 internal
10
10
9.4
9.4
9.4
2.9
2.9
2.9
2.9
2.9
2.9
-2.1
-2.1
-2.1
0.4
0.4
0.4
Setup time, AFSR0 input to ACLKR0 external input(3)
Setup time, AFSR0 input to ACLKX0 external input(4)
Setup time, AFSX0 input to ACLKX0 external input
Setup time, AFSR0 input to ACLKR0 external output(3)
Setup time, AFSR0 input to ACLKX0 external output(4)
Setup time, AFSX0 input to ACLKX0 external output
Hold time, AFSR0 input after ACLKR0 internal(3)
Hold time, AFSR0 input after ACLKX0 internal(4)
Hold time, AFSX0 input after ACLKX0 internal
Hold time, AFSR0 input after ACLKR0 external input(3)
Hold time, AFSR0 input after ACLKX0 external input(4)
Hold time, AFSX0 input after ACLKX0 external input
5
tsu(AFSRX-ACLKRX)
ns
6
th(ACLKRX-AFSRX)
ns
Hold time, AFSR0 input after ACLKR0 external
output(3)
0.4
0.4
Hold time, AFSR0 input after ACLKX0 external
output(4)
Hold time, AFSX0 input after ACLKX0 external output
Setup time, AXR0[n] input to ACLKR0 internal(3)
Setup time, AXR0[n] input to ACLKX0 internal(4)
Setup time, AXR0[n] input to ACLKR0 external input(3)
Setup time, AXR0[n] input to ACLKX0 external input(4)
0.4
9.4
9.4
2.9
2.9
7
tsu(AXR-ACLKRX)
ns
Setup time, AXR0[n] input to ACLKR0 external
output(3)
2.9
2.9
Setup time, AXR0[n] input to ACLKX0 external
output(4)
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Peripheral Information and Electrical Specifications
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