OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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6.15.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 6-44 and Table 6-45 assume testing over recommended operating conditions (see Figure 6-33 and
Figure 6-34).
Table 6-44. McASP1 Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Cycle time, AHCLKR1 external, AHCLKR1 input
Cycle time, AHCLKX1 external, AHCLKX1 input
Pulse duration, AHCLKR1 external, AHCLKR1 input
Pulse duration, AHCLKX1 external, AHCLKX1 input
Cycle time, ACLKR1 external, ACLKR1 input
20
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
20
10
2
3
4
ns
ns
ns
10
greater of 2P or 20
Cycle time, ACLKX1 external, ACLKX1 input
greater of 2P or 20
Pulse duration, ACLKR1 external, ACLKR1 input
Pulse duration, ACLKX1 external, ACLKX1 input
Setup time, AFSR1 input to ACLKR1 internal(3)
Setup time, AFSR1 input to ACLKX1 internal(4)
Setup time, AFSX1 input to ACLKX1 internal
10
10
10.4
10.4
10.4
2.6
Setup time, AFSR1 input to ACLKR1 external input(3)
Setup time, AFSR1 input to ACLKX1 external input(4)
Setup time, AFSX1 input to ACLKX1 external input
Setup time, AFSR1 input to ACLKR1 external output(3)
Setup time, AFSR1 input to ACLKX1 external output(4)
Setup time, AFSX1 input to ACLKX1 external output
Hold time, AFSR1 input after ACLKR1 internal(3)
Hold time, AFSR1 input after ACLKX1 internal(4)
Hold time, AFSX1 input after ACLKX1 internal
Hold time, AFSR1 input after ACLKR1 external input(3)
Hold time, AFSR1 input after ACLKX1 external input(4)
Hold time, AFSX1 input after ACLKX1 external input
5
tsu(AFSRX-ACLKRX)
2.6
ns
2.6
2.6
2.6
2.6
-2.6
-2.6
-2.6
0.3
0.3
6
th(ACLKRX-AFSRX)
ns
0.3
Hold time, AFSR1 input after ACLKR1 external
output(3)
0.3
0.3
Hold time, AFSR1 input after ACLKX1 external
output(4)
Hold time, AFSX1 input after ACLKX1 external output
Setup time, AXR1[n] input to ACLKR1 internal(3)
Setup time, AXR1[n] input to ACLKX1 internal(4)
Setup time, AXR1[n] input to ACLKR1 external input(3)
Setup time, AXR1[n] input to ACLKX1 external input(4)
0.3
10.4
10.4
2.6
2.6
7
tsu(AXR-ACLKRX)
ns
Setup time, AXR1[n] input to ACLKR1 external
output(3)
2.6
2.6
Setup time, AXR1[n] input to ACLKX1 external
output(4)
(1) ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(4) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
138
Peripheral Information and Electrical Specifications
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