OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-39. McASP Registers Accessed Through Peripheral Configuration Port (continued)
Offset
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
Acronym
Register Description
ADDRESS
ADDRESS
ADDRESS
78h
7Ch
80h
84h
88h
8Ch
ACh
0x01D0 0078
0x01D0 007C
0x01D0 0080
0x01D0 0084
0x01D0 0088
0x01D0 008C
0x01D0 00A0
0x01D0 4078
0x01D0 407C
0x01D0 4080
0x01D0 4084
0x01D0 4088
0x01D0 408C
0x01D0 40A0
0x01D0 8078 RTDM
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
0x01D0 807C RINTCTL
0x01D0 8080 RSTAT
0x01D0 8084 RSLOT
0x01D0 8088 RCLKCHK
0x01D0 808C REVTCTL
0x01D0 80A0 XGBLCTL
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
Transmitter global control register. Alias of GBLCTL,
only transmit bits are affected - allows transmitter to be
reset independently from receiver
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
100h
0x01D0 00A4
0x01D0 00A8
0x01D0 40A4
0x01D0 40A8
0x01D0 80A4 XMASK
0x01D0 80A8 XFMT
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
0x01D0 00AC 0x01D0 40AC 0x01D0 80AC AFSXCTL
0x01D0 00B0
0x01D0 00B4
0x01D0 00B8
0x01D0 40B0
0x01D0 40B4
0x01D0 40B8
0x01D0 80B0 ACLKXCTL
0x01D0 80B4 AHCLKXCTL
0x01D0 80B8 XTDM
Transmit high-frequency clock control register
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
Transmitter status register
0x01D0 00BC 0x01D0 40BC 0x01D0 80BC XINTCTL
0x01D0 00C0
0x01D0 00C4
0x01D0 00C8
0x01D0 40C0
0x01D0 40C4
0x01D0 40C8
0x01D0 80C0 XSTAT
0x01D0 80C4 XSLOT
0x01D0 80C8 XCLKCHK
Current transmit TDM time slot register
Transmit clock check control register
Transmitter DMA event control register
0x01D0 00CC 0x01D0 40CC 0x01D0 80CC XEVTCTL
0x01D0 0100
0x01D0 0104
0x01D0 0108
0x01D0 010C
0x01D0 0110
0x01D0 0114
0x01D0 0118
0x01D0 011C
0x01D0 0120
0x01D0 0124
0x01D0 0128
0x01D0 012C
0x01D0 0130
0x01D0 0134
0x01D0 0138
0x01D0 4100
0x01D0 4104
0x01D0 4108
0x01D0 410C
0x01D0 4110
0x01D0 4114
0x01D0 4118
0x01D0 411C
0x01D0 4120
0x01D0 4124
0x01D0 4128
0x01D0 412C
0x01D0 4130
0x01D0 4134
0x01D0 4138
0x01D0 8100 DITCSRA0
0x01D0 8104 DITCSRA1
0x01D0 8108 DITCSRA2
0x01D0 810C DITCSRA3
0x01D0 8110 DITCSRA4
0x01D0 8114 DITCSRA5
0x01D0 8118 DITCSRB0
0x01D0 811C DITCSRB1
0x01D0 8120 DITCSRB2
0x01D0 8124 DITCSRB3
0x01D0 8128 DITCSRB4
0x01D0 812C DITCSRB5
0x01D0 8130 DITUDRA0
0x01D0 8134 DITUDRA1
0x01D0 8138 DITUDRA2
Left (even TDM time slot) channel status register (DIT
mode) 0
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
Left (even TDM time slot) channel status register (DIT
mode) 1
Left (even TDM time slot) channel status register (DIT
mode) 2
Left (even TDM time slot) channel status register (DIT
mode) 3
Left (even TDM time slot) channel status register (DIT
mode) 4
Left (even TDM time slot) channel status register (DIT
mode) 5
Right (odd TDM time slot) channel status register (DIT
mode) 0
Right (odd TDM time slot) channel status register (DIT
mode) 1
Right (odd TDM time slot) channel status register (DIT
mode) 2
Right (odd TDM time slot) channel status register (DIT
mode) 3
Right (odd TDM time slot) channel status register (DIT
mode) 4
Right (odd TDM time slot) channel status register (DIT
mode) 5
Left (even TDM time slot) channel user data register
(DIT mode) 0
Left (even TDM time slot) channel user data register
(DIT mode) 1
Left (even TDM time slot) channel user data register
(DIT mode) 2
132
Peripheral Information and Electrical Specifications
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