XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-67. Bit Descriptions – Power Management Capabilities Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Device-specific initialization. This bit returns 0 when read, which indicates that the
XIO3130 does not require special initialization beyond the standard PCI configuration
header before a generic class driver is able to use it.
5
DSI
r
4
3
RSVD
r
r
Reserved. When read, this bit returns zero.
PME clock. This bit returns zero, which indicates that the PCI clock is not needed to
generate PME.
PME_CLK
Power management version. This field returns 3’b011, which indicates Revision 1.2
compatibility.
2:0
PM_VERSION
r
4.3.33 Power Management Control/Status Register
This register determines and changes the current power state of the downstream port.
PCI register offset:
Register type:
54h
Read/Write; Read Only; Clear by a Write of One; Hardware Update; Sticky
0008h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Table 4-68. Bit Descriptions – Power Management Control/Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
PME status. PME events are generated due to PCI Hot Plug events. This bit reflects the
PME status regardless of the state of PME_EN.
0 – No PME event pending
1 – PME event pending
15
PME_STAT
rcuh
This bit is reset with GRST.
Data scale. This 2-bit field returns 0s when read since the XIO3130 does not use the Data
register.
14:13
12:9
DATA_SCALE
DATA_SEL
r
r
Data select. This 4-bit field returns 0s when read since the XIO3130 does not use the Data
register.
PME enable. This bit enables PME/WAKE signaling, even though the XIO3130 never
generates WAKE .
0 – Disable PME signaling.
8
PME_EN
rwh
1 – Enable PME signaling.
This bit is reset with GRST.
7:4
3
RSVD
NO_SOFT_RST
RSVD
r
r
r
Reserved. When read, these bits return zeros.
No Soft Reset. This bit controls whether the transition from D3hot to D0 resets the state
according to PCI Power Management Specification Revision 1.2. This bit is hardwired to
1’b1.
0 – D3hot to D0 transition causes reset.
1 – D3hot to D0 transition does not cause reset.
Reserved. When read, this bit returns zero.
2
Power state. This 2-bit field is used to determine the current power state of the function and
to set the function into a new power state. This field is encoded as follows:
00 = D0
01 = D1
10 = D2
11 = D3hot
1:0
PWR_STATE
rw
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XIO3130 Configuration Register Space
101
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