XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
4.3.24 I/O Base Upper 16 Bits Register
This read/write register specifies the upper 16 bits of the I/O Base register.
PCI register offset:
Register type:
30h
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-64. Bit Descriptions – I/O Base Upper 16 Bits Register
BIT
15:0
FIELD NAME
ACCESS
DESCRIPTION
I/O base upper 16 bits. This field defines the upper 16 bits of the bottom address of the I/O
address range that is used to determine when to forward I/O transactions downstream.
IOBASE
rw
4.3.25 I/O Limit Upper 16 Bits Register
This read/write register specifies the upper 16 bits of the I/O Limit register.
PCI register offset:
Register type:
32h
Read/Write
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-65. Bit Descriptions – I/O Limit Upper 16 Bits Register
BIT
15:0
FIELD NAME
ACCESS
DESCRIPTION
I/O limit upper 16 bits. This field defines the upper 16 bits of the top address of the I/O
address range that is used to determine when to forward I/O transactions downstream.
IOLIMIT
rw
4.3.26 Capabilities Pointer Register
This read-only register provides a pointer into the PCI configuration header, which is where the PCI power
management block resides. Since the PCI power management registers begin at 50h, this register is
hardwired to 50h.
PCI register offset:
Register type:
34h
Read only
50h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
Copyright © 2007–2010, Texas Instruments Incorporated
XIO3130 Configuration Register Space
97
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