XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
4.3.38 MSI Message Control Register
This register is used to control the sending of MSI messages.
PCI register offset:
Register type:
72h
Read/Write; Read Only
0080h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Table 4-70. Bit Descriptions – MSI Message Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:8
RSVD
r
64-bit message capability. This bit is read-only 1, which indicates that the XIO3130 downstream
port supports 64-bit MSI message addressing.
7
64CAP
r
Multiple message enable. This field indicates the number of distinct messages that the XIO3130
downstream port is allowed to generate.
000 – 1 message
001 – 2 messages
010 – 4 messages
011 – 8 messages
100 – 16 messages
101 – 32 messages
110 – Reserved
6:4
MM_EN
rw
111 – Reserved
Multiple message capabilities. This field indicates the number of distinct messages that the
XIO3130 downstream port can generate. This field is read-only 000, which indicates that the
downstream port can signal one interrupt.
3:1
0
MM_CAP
MSI_EN
r
MSI Enable. This bit is used to enable MSI interrupt signaling. The software must enable MSI
signaling for the XIO3130 downstream port to send MSI messages.
rw
0 – MSI signaling is prohibited
1 – MSI signaling is enabled
4.3.39 MSI Message Address Register
This register contains the lower 32 bits of the address that an MSI message shall be written to when an
interrupt is to be signaled.
PCI register offset:
Register type:
74h
Read/Write; Read Only
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Copyright © 2007–2010, Texas Instruments Incorporated
XIO3130 Configuration Register Space
103
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