XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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4.3.34 Power Management Bridge Support Extension Register
This read-only register is used to indicate to the host software what the state of the downstream port’s
secondary bus will be when the downstream port is placed in D3.
PCI register offset:
Register type:
56h
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 4-69. Bit Descriptions – PM Bridge Support Extension Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Bus power/Clock control enable. This bit is read-only zero. This bit does not apply to PCI
Express.
7
BPCC
r
6
BSTATE
RSVD
r
r
B2/B3 support. This bit is read-only zero. This bit does not apply to PCI Express.
Reserved. When read, these bits return zeros.
5:0
4.3.35 Power Management Data Register
The read-only register is not applicable to the XIO3130 and returns 00h when read.
PCI register offset:
Register type:
57h
Read only
00h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.36 MSI Capability ID Register
This read-only register identifies the linked list item as the register for Message Signaled Interrupts
Capabilities. The register returns 05h when read.
PCI register offset:
Register type:
70h
Read only
05h
Default value:
BIT NUMBER
RESET STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
1
4.3.37 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130. This register reads 80h, which points to the Subsystem ID and Subsystem Vendor ID
Capabilities registers.
PCI register offset:
Register type:
71h
Read only
80h
Default value:
102
XIO3130 Configuration Register Space
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