XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-66. Bit Descriptions – Bridge Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Secondary bus reset. This bit is set when the software resets all devices downstream of the
XIO3130 downstream port. Setting this bit causes the downstream port to send a reset downstream
via a training sequence.
6
SRST
rw
0 – Downstream port not in Reset state
1 – Downstream port in Reset state
5
4
MAM
r
Master abort mode. This bit is hardwired to zero. This bit does not apply to PCI Express.
VGA 16-bit decode. This bit enables the XIO3130 downstream port to provide full 16-bit decoding
for VGA I/O addresses. This bit only has meaning if the VGA enable bit is set.
VGA16
rw
0 – Ignore address bits [15:10] when decoding VGA I/O addresses.
1 – Decode address bits [15:10] when decoding VGA I/O addresses.
VGA enable. This bit modifies the response by the XIO3130 downstream port to VGA-compatible
addresses. If this bit is set, the XIO3130 downstream port positively decodes and forwards the
following accesses on the primary interface to the secondary interface (and, conversely, blocks the
forwarding of these addresses from the secondary to primary interface):
•＝ Memory accesses in the range 000A 0000h to 000BFFFFh
•＝ I/O addresses in the first 64KB of the I/O address space (address bits [31:16] are 0000h.) and
where address bits [9:0] are in the range 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA
address aliases; address bits [15:10] may possess any value and are not used in the
decoding).
If the VGA Enable bit is set, forwarding of VGA addresses is independent of the value of the ISA
Enable bit (located in the Bridge Control register), the I/O address range and memory address
ranges defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the
Pre-fetchable Memory Base and Limit registers of the bridge. Forwarding of VGA addresses is
qualified by the I/O Enable and Memory Enable bits in the Command register.
3
VGA
rw
0 – Do not forward VGA-compatible memory and I/O addresses from the primary to secondary
interface unless they are enabled for forwarding by the defined I/O and memory address
ranges.
1 – Forward VGA-compatible memory and I/O addresses from the primary interface to the
secondary interface (if the I/O Enable and Memory Enable bits are set) independent of the I/O
and memory address ranges and independent of the ISA Enable bit.
ISA enable. This bit modifies the response by the XIO3130 downstream port to ISA I/O addresses.
This bit applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and
are in the first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the
bridge blocks any forwarding from primary to secondary of I/O transactions addressing the last 768
bytes in each 1 KB block. In the opposite direction (secondary to primary), I/O transactions are
forwarded if they address the last 768 bytes in each 1K block.
2
ISA
rw
0 – Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O
Limit registers.
1 – Forward upstream ISA I/O addresses in the address range defined by the I/O Base and I/O
Limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1 KB
block).
SERR enable. This bit controls the forwarding of system error events upstream from the secondary
interface to the primary interface. The XIO3130’s downstream port forwards system error events
upstream when:
•＝ This bit is set.
•＝ The SERR enable bit in the downstream port command register is set.
1
0
SERR_EN
PERR_EN
rw
rw
•＝ A nonfatal or fatal error condition is detected on the secondary interface (i.e., the PCI Express
interface).
0 – Disable the reporting of nonfatal errors and fatal errors.
1 – Enable the reporting of nonfatal errors and fatal errors.
Parity error response enable. For PCI Express, this bit controls responses to poisoned TLPs
received on the downstream port.
0 – Disable responses to poisoned TLPs.
1 – Enable responses to poisoned TLPs.
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XIO3130 Configuration Register Space
99
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