MSP430F530x, MSP430F5310
SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 11)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
fSCL
SCL clock frequency
2.2 V/3 V
2.2 V/3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
f
f
f
f
SCL ≤ 100 kHz
SCL > 100 kHz
SCL ≤ 100 kHz
SCL > 100 kHz
tHD,STA
Hold time (repeated) START
µs
tSU,STA
Setup time for a repeated START
2.2 V/3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V/3 V
2.2 V/3 V
ns
ns
250
4.0
0.6
50
fSCL ≤ 100 kHz
SCL > 100 kHz
tSU,STO
Setup time for STOP
2.2 V/3 V
µs
f
2.2 V
3 V
600
ns
tSP
Pulse width of spikes suppressed by input filter
50
600
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 11. I2C Mode Timing
58
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