MSP430F530x, MSP430F5310
SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011
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USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 9 and Figure 10)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
11
8
TYP
MAX UNIT
PMMCOREV = 0
ns
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE low to clock
2.4 V
3 V
7
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
ns
ns
ns
6
1.8 V
3 V
3
3
STE lag time, Last clock to STE high
2.4 V
3 V
3
3
1.8 V
3 V
66
ns
50
STE access time, STE low to SOMI data out
2.4 V
3 V
36
ns
30
1.8 V
3 V
30
ns
23
STE disable time, STE high to SOMI high
impedance
2.4 V
3 V
16
ns
13
1.8 V
3 V
5
5
2
2
5
5
5
5
ns
ns
ns
SIMO input data setup time
SIMO input data hold time
2.4 V
3 V
1.8 V
3 V
tHD,SI
2.4 V
3 V
ns
UCLK edge to SOMI valid,
CL = 20 pF
PMMCOREV = 0
1.8 V
76
ns
3 V
2.4 V
3 V
60
(2)
tVALID,SO
SOMI output data valid time
UCLK edge to SOMI valid,
CL = 20 pF
PMMCOREV = 3
44
ns
40
1.8 V
3 V
18
12
10
8
CL = 20 pF
PMMCOREV = 0
ns
ns
(3)
tHD,SO
SOMI output data hold time
2.4 V
3 V
CL = 20 pF
PMMCOREV = 3
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 7 and Figure 8.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 7 and Figure 8.
56
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