MSP430FR573x
MSP430FR572x
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Port P1, P1.6 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P1REN.x
P1DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
From module 3
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1SEL0.x
P1SEL1.x
P1IN.x
Bus
Keeper
EN
D
To modules
Table 45. Port P1 (P1.6 to P1.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
6
P1.6 (I/O)
I: 0; O: 1
0
0
(1)
TB1.CCI1A
0
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
(1)
TB1.1
(2)
UCB0SIMO/UCB0SDA
TA0.CCI0A
X
0
TA0.0
1
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
7
P1.7 (I/O)
I: 0; O: 1
(1)
TB1.CCI2A
0
1
(1)
TB1.2
(3)
UCB0SOMI/UCB0SCL
TA1.CCI0A
X
0
1
TA1.0
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_B0 module.
(3) Direction controlled by eUSCI_A0 module.
Copyright © 2011–2012, Texas Instruments Incorporated
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