MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Table 43. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
(1)
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
0
P1.0 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
0
0
0
1
0
1
0
1
1
0
DMAE0
RTCCLK
(2) (3)
A0
(2) (4)
CD0
X
1
1
(2) (3)
VeREF-
P1.1 (I/O)
TA0.CCI2A
TA0.2
P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
1
I: 0; O: 1
0
0
0
1
0
1
0
1
TA1CLK
CDOUT
1
1
0
1
(2) (3)
A1
(2) (4)
CD1
X
(2) (3)
VeREF+
P1.2 (I/O)
TA1.CCI1A
TA1.1
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
2
I: 0; O: 1
0
0
0
1
0
1
0
1
TA0CLK
CDOUT
1
1
0
1
(2) (3)
A2
X
(2) (4)
CD2
(1) This pin is tied to AVSS for YFF package types. All functions are therefore tied to ground at the pin.
(2) Setting P1SEL1.x and P1SEL0.x disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Not available on all devices and package types.
(4) Setting the CDPD.x bit of the comparator disables the output driver as well as the input Schmitt trigger to prevent parasitic cross
currents when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically
disables output driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
70
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