MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Table 44. Port P1 (P1.3 to P1.5) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.3/TA1.2/UCB0STE/A3/CD3
3
P1.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
0
0
0
1
0
1
(1)
UCB0STE
X
1
1
0
0
1
0
(2) (3)
A3
X
(2) (4)
CD3
P1.4/TB0.1/UCA0STE/A4/CD4
P1.5/TB0.2/UCA0CLK/A5/CD5
4
5
P1.4 (I/O)
TB0.CCI1A
TB0.1
I: 0; O: 1
0
1
0
1
(5)
UCA0STE
X
1
1
0
0
1
0
(2) (3)
A4
X
(2) (4)
CD4
P1.5(I/O)
TB0.CCI2A
TB0.2
I: 0; O: 1
0
1
0
1
(5)
UCA0CLK
X
1
1
0
1
(2) (3)
A5
X
(2) (4)
CD5
(1) Direction controlled by eUSCI_B0 module.
(2) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Not available on all devices and package types.
(4) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit
(5) Direction controlled by eUSCI_A0 module.
72
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