MSP430FR573x
MSP430FR572x
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Port P2, P2.5 to P2.6, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 48. Port P2 (P2.5 to P2.6) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
(1)
P2.5/TB0.0/UCA1TXD/UCA1SIMO
5
P2.5(I/O)
I: 0; O: 1
0
0
(1)
TB0.CCI0B
0
1
0
1
(1)
TB0.0
(1)
(2)
UCA1TXD/UCA1SIMO
X
1
0
0
0
(1)
P2.6/TB1.0/UCA1RXD/UCA1SOMI
6
P2.6(I/O)
I: 0; O: 1
(1)
TB1.CCI0B
0
1
0
1
1
0
(1)
TB1.0
(1)
(2)
UCA1RXD/UCA1SOMI
X
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_A1 module.
Copyright © 2011–2012, Texas Instruments Incorporated
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