MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Table 47. Port P2 (P2.3 to P2.4) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.3/TA0.0/UCA1STE/A6/CD10
3
P2.3 (I/O)
TA0.CCI0B
TA0.0
I: 0; O: 1
0
0
0
1
0
1
(1)
UCA1STE
X
1
1
0
0
1
0
(2) (3)
A6
X
(2) (4)
CD10
P2.4/TA1.0/UCA1CLK/A7/CD11
4
P2.4 (I/O)
TA1.CCI0B
TA1.0
I: 0; O: 1
0
1
0
1
(1)
UCA1CLK
X
1
1
0
1
(2) (3)
A7
X
(2) (4)
CD11
(1) Direction controlled by eUSCI_A1 module.
(2) Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Not available on all devices and package types.
(4) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
76
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