MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P2REN.x
P2DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
From module 3
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 46. Port P2 (P2.0 to P2.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
0
P2.0 (I/O)
I: 0; O: 1
0
0
1
0
1
0
1
0
1
0
1
0
1
(1)
TB2.CCI0A
0
1
0
1
1
0
0
1
1
0
0
1
1
(1)
TB2.0
(2)
UCA0TXD/UCA0SIMO
TB0CLK
X
0
ACLK
1
1
2
P2.1 (I/O)
I: 0; O: 1
(1)
TB2.CCI1A
0
1
(1)
TB2.1
(2)
UCA0RXD/UCA0SOMI
TB0.CCI0A
X
0
TB0.0
1
P2.2 (I/O)
I: 0; O: 1
(1)
TB2.CCI2A
0
(1)
TB2.2
1
(3)
UCB0CLK
X
(1)
TB1.CCI0A
0
1
(1)
TB1.0
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_A0 module.
(3) Direction controlled by eUSCI_B0 module.
74
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