MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
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Table 12. Port Mapping, Mnemonics and Functions (continued)
VALUE
19
PxMAPy MNEMONIC
Reserved
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
Reserved for test purposes. Do not use this setting.
20-30
Reserved
None
DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals.
31 (0FFh)(1)
PM_ANALOG
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
which results in a read out value of 31.
Table 13. Default Mapping
PxMAPy
MNEMONIC
PIN
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_UCB0STE,
PM_UCA0CLK
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),
USCI_A0 clock input/output (direction controlled by USCI)
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
PM_UCB0SIMO,
PM_UCB0SDA
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0SOMI,
PM_UCB0SCL
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0CLK,
PM_UCA0STE
USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCA0TXD,
PM_UCA0SIMO
USCI_A0 UART TXD (direction controlled by USCI - output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0RXD,
PM_UCA0SOMI
USCI_A0 UART RXD (direction controlled by USCI - input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
P2.6/P2MAP6/R03
PM_NONE
PM_NONE
-
-
DVSS
DVSS
P2.7/P2MAP7/LCDREF/R13
Oscillator and System Clock
The clock system in the MSP430F663x family of devices is supported by the Unified Clock System (UCS)
module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not
supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency
oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal
oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power
consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a
digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The
internal DCO provides a fast turn-on clock source and stabilizes in 3 µs (typical). The UCS module provides the
following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally-
controlled oscillator DCO.
•
•
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to
ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
24
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