欢迎访问ic37.com |
会员登录 免费注册
发布采购

MSP430F6630IPZR 参数 Datasheet PDF下载

MSP430F6630IPZR图片预览
型号: MSP430F6630IPZR
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号微控制器 [MIXED SIGNAL MICROCONTROLLER]
分类和应用: 微控制器
文件页数/大小: 116 页 / 1284 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号MSP430F6630IPZR的Datasheet PDF文件第18页浏览型号MSP430F6630IPZR的Datasheet PDF文件第19页浏览型号MSP430F6630IPZR的Datasheet PDF文件第20页浏览型号MSP430F6630IPZR的Datasheet PDF文件第21页浏览型号MSP430F6630IPZR的Datasheet PDF文件第23页浏览型号MSP430F6630IPZR的Datasheet PDF文件第24页浏览型号MSP430F6630IPZR的Datasheet PDF文件第25页浏览型号MSP430F6630IPZR的Datasheet PDF文件第26页  
MSP430F663x  
SLAS566C JUNE 2010REVISED AUGUST 2012  
www.ti.com  
Table 10. JTAG Pin Requirements and Functions  
DEVICE SIGNAL  
PJ.3/TCK  
DIRECTION  
FUNCTION  
JTAG clock input  
JTAG state control  
JTAG data input, TCLK input  
JTAG data output  
Enable JTAG pins  
External reset  
IN  
IN  
PJ.2/TMS  
PJ.1/TDI/TCLK  
PJ.0/TDO  
IN  
OUT  
IN  
TEST/SBWTCK  
RST/NMI/SBWTDIO  
VCC  
IN  
Power supply  
VSS  
Ground supply  
Spy-Bi-Wire Interface  
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-  
Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire  
interface pin requirements are shown in Table 11. For further details on interfacing to development tools and  
device programmers, see the MSP430(tm) Hardware Tools User's Guide (SLAU278). For a complete description  
of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface  
(SLAU320).  
Table 11. Spy-Bi-Wire Pin Requirements and Functions  
DEVICE SIGNAL  
TEST/SBWTCK  
RST/NMI/SBWTDIO  
VCC  
DIRECTION  
IN  
FUNCTION  
Spy-Bi-Wire clock input  
Spy-Bi-Wire data input/output  
Power supply  
IN, OUT  
VSS  
Ground supply  
Flash Memory  
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the  
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the  
flash memory include:  
Flash memory has n segments of main memory and four segments of information memory (A to D) of  
128 bytes each. Each segment in main memory is 512 bytes in size.  
Segments 0 to n may be erased in one step, or each segment may be individually erased.  
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also  
called information memory.  
Segment A can be locked separately.  
RAM Memory  
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,  
however all data is lost. Features of the RAM memory include:  
RAM memory has n sectors. The size of a sector can be found in Memory Organization.  
Each sector 0 to n can be complete disabled, however data retention is lost.  
Each sector 0 to n automatically enters low power retention mode when possible.  
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.  
Backup RAM Memory  
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during  
operation from a backup supply if the Battery Backup System module is implemented.  
There are 8 bytes of Backup RAM available on MSP430F663x. It can be wordwise accessed via the control  
registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.  
22  
Copyright © 2010–2012, Texas Instruments Incorporated  
 
 复制成功!