MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Digital I/O
There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete, and port PJ contains four
individual I/O ports.
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All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Programmable drive strength on all ports.
Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
Read/write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).
Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.
Table 12. Port Mapping, Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
PM_NONE
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
None
DVSS
PM_CBOUT
-
Comparator_B output
1
2
PM_TB0CLK
Timer TB0 clock input
-
PM_ADC12CLK
PM_DMAE0
-
ADC12CLK
-
DMAE0 Input
-
PM_SVMOUT
SVM output
3
Timer TB0 high impedance input
TB0OUTH
PM_TB0OUTH
-
4
5
PM_TB0CCR0B
PM_TB0CCR1B
PM_TB0CCR2B
PM_TB0CCR3B
PM_TB0CCR4B
PM_TB0CCR5B
PM_TB0CCR6B
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCB0STE
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0STE
PM_MCLK
Timer TB0 CCR0 capture input CCI0B
Timer TB0 CCR1 capture input CCI1B
Timer TB0 CCR2 capture input CCI2B
Timer TB0 CCR3 capture input CCI3B
Timer TB0 CCR4 capture input CCI4B
Timer TB0 CCR5 capture input CCI5B
Timer TB0 CCR6 capture input CCI6B
Timer TB0: TB0.0 compare output Out0
Timer TB0: TB0.1 compare output Out1
Timer TB0: TB0.2 compare output Out2
Timer TB0: TB0.3 compare output Out3
Timer TB0: TB0.4 compare output Out4
Timer TB0: TB0.5 compare output Out5
Timer TB0: TB0.6 compare output Out6
6
7
8
9
10
USCI_A0 UART RXD (Direction controlled by USCI - input)
11
12
13
14
15
16
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (Direction controlled by USCI - output)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
USCI_B0 SPI slave out master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
17
18
-
MCLK
Reserved
Reserved for test purposes. Do not use this setting.
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