4.0 Registers (Continued)
4.15 PHY ADDRESS REGISTER (PAR)
Address 19h
Bit
Bit Name
Default
Description
4:0
PHYADDR[4:0] (PHYAD[4:0]), RW PHY ADDRESS BITS 4:0: The values of the PHYAD[4:0] pins are
latched to this register at power-up/reset. See Section 2.8 for the
description of these pins.
The first PHY address bit transmitted or received over the serial MII is
the MSB of the address (bit 4). A station management entity must know
the address of each PHY it is connected to in order to gain access.
A PHY address of <00000> will cause the Isolate bit of the BMCR (bit
10, register address 00h) to be set.
Version A
National Semiconductor
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TI [ TEXAS INSTRUMENTS ]
