4.0 Registers (Continued)
4.11 RECEIVE ERROR COUNTER REGISTER (RECR)
Address 15h
Bit
Bit Name
Default
Description
15:0 RXERCNT[15:0] <0000h>, RW/SC RX_ER COUNTER: This 16-bit counter is incremented for each packet
in which a receive error is detected. If there are one or more receiver
error conditions during a valid packet reception (i.e. no collision occurred
during packet reception), the counter is incremented once at the end of
packet reception. This counter rolls over when full.
4.12 SILICON REVISION REGISTER (SRR)
Address 16h
Bit
Bit Name
Default
Description
15:0
SIREV[15:0]
<0001h>, RO/P Silicon Revision Number: This register contains the DP83840A
device’s silicon revision code. The value will be incremented for each
new major revision of the silicon.
4.13 PCS CONFIGURATION REGISTER (PCR)
Address 17h
Bit
Bit Name
Default
Description
15
NRZI_EN
1, RW
NRZI ENABLE:
1 = NRZI encoding and decoding of the 100Mb/s transmit and receive
data streams
0 = NRZI encoding and decoding disabled
DESCRAMBLER TIMEOUT SELECT:
1 = Descrambler Timer set to 2 ms
0 = Descrambler Timer set to 722 µs
14 DESCR_TO_SEL
0, RW
The Descrambler Timer selects the interval over which a minimum
number of IDLES are required to be received to maintain descrambler
synchronization. The default time of 722 µs supports 100BASE-X
compliant applications.
A timer timeout indicates a loss of descrambler synchronization which
causes the descrambler to restart its operation by immediately looking
for IDLEs.
The 2 ms option allows applications with Maximum Transmission Units
(packet sizes) larger than IEEE 802.3 to maintain descrambler
synchronization
applications.)
(i.e.
Token
Ring/Fast-Ethernet
switch/router
13 DESCR_TO_DIS
0, RW
DESCRAMBLER TIMEOUT DISABLE:
1 = Timeout timer in the descrambler section of the receiver disabled
0 = Timeout timer enabled
12
REPEATER
(Pin #47), RW
REPEATER/NODE MODE:
1 = Repeater mode
0 = Node mode
In repeater mode the Carrier Sense (CRS) output from the DP83840A is
asserted due to receive activity only. In node mode, and not configured
for Full Duplex operation, CRS is asserted due to either receive or
transmit activity.
The value of the REPEATER pin 47 (set by a pull-up or pull-down
resistor, typically 4.7 kΩ) is latched into this bit at power-up/reset.
Version A
National Semiconductor
50
TI [ TEXAS INSTRUMENTS ]
