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DP83840AVCE 参数 Datasheet PDF下载

DP83840AVCE图片预览
型号: DP83840AVCE
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100 Mb / s的以太网物理层 [10/100 Mb/s Ethernet Physical Layer]
分类和应用: 电信集成电路电信电路信息通信管理以太网局域网(LAN)标准
文件页数/大小: 91 页 / 682 K
品牌: TI [ TEXAS INSTRUMENTS ]
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4.0 Registers (Continued)  
4.8 AUTO-NEGOTIATION EXPANSION REGISTER (ANER)  
Address 06h  
Bit  
15:5  
4
Bit Name  
Reserved  
MLF  
Default  
0, RO  
Description  
RESERVED: Always 0.  
0, RO/L  
MULTIPLE LINK FAULT:  
1 = Multiple Link Fault--indicates that it was not possible to resolve the  
connection because the 10BASE-T Link Integrity Test function and/  
or the 100BASE-X Link Integrity Monitor indicated a valid link yet  
both or neither of these functions maintained a valid link according to  
Auto-Negotiation specification. This bit generally indicates that the  
receive channel is improperly functioning or improperly connected.  
0 = No Multiple Link Fault  
3
2
1
LP_NP_ABLE  
NP_ABLE  
0, RO  
0, RO/P  
0, RO  
LINK PARTNER NEXT PAGE ABLE: Status indicating if the Link  
Partner supports Next Page negotiation. ndicates that the Link  
Partner supports Next Page.  
NEXT PAGE ABLE: Indicas if this s able o send additional  
“Next Pages”. The DP83840A t Next ge Able, o this bit is always  
zero.  
PAGE_RX  
LINK CODE WORD PAGE RECEIVD: This bit is set when a new Link  
Code Word Page has eived. is bit is automatically cleared  
when the Auto-Negnk Partner Ability Register (ANLPAR  
register 05) is read gemt.  
0
LP_AN_ABLE  
0, RO  
LINK PARTR AU-NEGOTATION ABLE: A one in this bit  
indicates that think Paer spports Auto-Negotiation.  
4.9 DISCONNECT COUNTER REGISTER (DC
Address 12h  
Bit  
Bit Name  
Default  
Description  
15:0  
DCNT[15:0]  
<0000h>, RWSC DISCONNECT COUNTER: This 16-bit counter increments for each  
sconect event. Each time this DP83840A and its Link Partner are  
disconected from each other, the counter increments. This counter  
autoatically rolls over to 0000h.  
4.10 FALSE CARRIER SETER REGISTER (FCSCR)  
Address 13h  
Bit  
Default  
Description  
15:0  
F
00h>, RW/SC FALSE CARRIER EVENT COUNTER: This 16-bit counter increments  
for each false carrier event, that is, when carrier sense is asserted  
without J/K symbol detection. This counter freezes when full (at FFFFh).  
This counter represents the total number of false carrier events since  
the last management read. The Carrier Integrity Monitor uses its own  
counter to qualify whether the link is unstable.  
Version A  
National Semiconductor  
49  
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