3.12.3 Phaser Mode
The final mode of operation at 100 Mb/s is referred to as
the “Phaser” mode. This mode might be used for those
applications where the system design requires only the
clock recovery and clock generation functions of the
DP83840A. This is accomplished either by configuring the
BPALIGN pin (99) of the DP83840A to a logic high level
prior to power-up/hardware reset or by setting the
BP_ALlGN bit (bit 12) of the LBREMR register (address
18h).
In “Phaser” mode, all of the conditioning blocks in the
transmit and receive sections of the 100BASE-X section
are bypassed (refer to Figures 4 and 5). Therefore,
whatever 5B data is presented to the MII transmit inputs
(TXD[3:0] and TX_ER) of the DP83840A is simply
serialized and output to the DP83223A twisted pair
transceiver to be sent out over the twisted pair cable.
Similarly, the 100BASE-X serial data received at the RD+/-
inputs of the DP83840A are shifted into 5-bit parallel words
and presented to the MII receive outputs RXD[3:0] and
RX_ER. All data, including Idles, passes through the
DP83840A unaltered other than for serial/parallel
conversions.
3.12.4 100BASE-FX Mode
The DP83840 will allow 100BASE-FX functionality by
bypassing the scrambler and descrambler. This can be
accomplished either through hardware configuration or via
software.
The hardware configuration is set simply by tying the
BPSCR pin (1) high with a 4.7k resistor and then cycling
power or resetting the DP83840A. The software setting is
accomplished by setting the BP_SCR bit (bit 13) of the
LBREMR register (address 18h) via MII serial
management.
3.13 Low Power Mode
The DP83840A supports two power modes of operation:
The first mode allows both the 10 Mb/s and 100 Mb/s
functions of the device to be powered-up. In this mode, the
DP83840A may be switched to and from 10 Mb/s and 100
Mb/s modes as desired by management or Auto-
Negotiation.
The second mode is a low power mode of operation which
only powers the 100 Mb/s portions of the DP83840A.
Neither 10 Mb/s nor Auto-Negotiation will function in this
mode. This mode is particularly useful in 100 Mb/s
repeater applications that do not utilize the 10 Mb/s or
Auto-Negotiation functions.
Depending on the system design parameters, setting all of
the DP83840A devices within a typical 12-port 100BASE-X
repeater implementation will save a total of between
500mA and 800mA for the system.
The selection between the two modes is determined by the
state of the LOWPWR pin (pin 3). When LOWPWR is high,
the low power mode is selected. When LOWPWR is low,
full functionality of the DP83840A is available.
Version A
41
National Semiconductor
TI [ TEXAS INSTRUMENTS ]
