欢迎访问ic37.com |
会员登录 免费注册
发布采购

DP83840AVCE 参数 Datasheet PDF下载

DP83840AVCE图片预览
型号: DP83840AVCE
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100 Mb / s的以太网物理层 [10/100 Mb/s Ethernet Physical Layer]
分类和应用: 电信集成电路电信电路信息通信管理以太网局域网(LAN)标准
文件页数/大小: 91 页 / 682 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号DP83840AVCE的Datasheet PDF文件第34页浏览型号DP83840AVCE的Datasheet PDF文件第35页浏览型号DP83840AVCE的Datasheet PDF文件第36页浏览型号DP83840AVCE的Datasheet PDF文件第37页浏览型号DP83840AVCE的Datasheet PDF文件第39页浏览型号DP83840AVCE的Datasheet PDF文件第40页浏览型号DP83840AVCE的Datasheet PDF文件第41页浏览型号DP83840AVCE的Datasheet PDF文件第42页  
3.0 Functional Description (Continued)  
Table III. Auto-Negotiation Mode Select  
AN1  
AN0  
Action  
Mode  
(Pin 46) (Pin 95)  
FORCED MODES  
0
1
M
M
0
PAR (19h) Bit 10 = 0, Bit 6 = 1, Bit 7= 0  
ANAR (04h) [8:5] = 021h  
Auto-Negotiation Disabled with Only Half-Duplex  
10BASE-T Forced (Note 2)  
PAR (19h) Bit 10 = 0, Bit 6 = 1, Bit 7= 1  
ANAR (04h) [8:5] = 041h  
Auto-Negotiation disabled with Only Full-Duplex  
10BASE-T Forced (Note 2)  
M
M
C
PAR (19h)) Bit 10 = 0, Bit 6 = 0, Bit 7= 0  
ANAR (04h) [8:5] = 081h  
Auto-Negotiation disabled with Only Half-Duplex  
100BASE-X Forced (Note 2)  
1
PAR (19h) Bit 10 = 0, Bit 6 = 0, Bit 7 = 1  
ANAR (04h) [8:5] = 101h  
Auto-Negotiation disabled with Only Full-Duplex  
100BASE-X Forcee 2)  
M
PAR (19h) Bit 10 = 0, Bit 6 = 0, Bit 7 = 1  
ANAR (04h) [8:5] = 181h  
Auto-Negotiatioed wiOnly Full-Duplex  
100BSE-X Fo
(Defauvertisent set 100BASE-X Half-  
Duplex an00BASE-X Full-Duplex)  
M
C
C
C
PAR (19h) Bit 10 = 0, Bit 6 = 0, Bit 7 = 1  
ANAR (04h) [8:5] = 141h  
gotiatiodibled with Only Full-Duplex  
E-X Forced  
ult adertisement set to 100BASE-X Full-  
plex an10BASE-T Full Duplex)  
PAR (19h) Bit 10 = 0, Bit 6 = 0, Bit 7 = 0  
ANAR (04h) [8:5] = 0A1h  
Autgotiation disabled with Only Half-Duplex  
100BASE-X Forced  
efault advertisement set to 100BASE-X Half-  
Duplex and 10BASE-T Half-Duplex)  
ADVERTISED MODES  
M
M
PAR (19h) Bit 10 1  
Auto-Negotiation Enabled for All DP83840A  
Possible Protocols (Note 2)  
ANAR (04h) [8:5] 1E1
0
0
PAR (19h) Bit 10 = 1  
Auto-Negotiation Enabled with Only Half-Duplex  
10BASE-T Available  
AAR 021h  
0
1
PAR (
Auto-Negotiation Enabled with Only Full-Duplex  
10BASE-T Available  
AR (0041h  
1
19h) Bi0 = 1  
Auto-Negotiation Enabled with Only Half-Duplex  
100BASE-X Available  
04h) [8:5] = 081h  
1
9h) Bit 10 = 1  
Auto-Negotiation Enabled with Only Full-Duplex  
100BASE-X Available  
R (04h) [8:5] = 101h  
C
C
1
1
PAR (19h) Bit 10 = 1  
Auto-Negotiation Enabled with 100BASE-X Full-  
Duplex and 10BASE- T Full Duplex Available  
ANAR (04h) [8:5] = 141h  
0
PAR (19h) Bit 10 = 1  
Auto-Negotiation Enabled with 100BASE-X Half-  
Duplex and 10BASE-T Half Duplex Available  
ANAR (04h) [8:5] = 0A1h  
C
C
PAR (19h) Bit 10 = 1  
Auto-Negotiation Enabled with 100BASE-X Full-  
Duplex and 100BASE-X Half Duplex Available  
ANAR (04h) [8:5] = 181h  
0
PAR (19h) Bit 10 = 1  
Auto-Negotiation Enabled with 10BASE-T Full-  
Duplex and 10BASE-T Half Duplex Available  
ANAR (04h) [8:5] = 061h  
Note 1:“M” indicates logic mid level (Vcc/2), “1” indicates logic high level, “0” indicates logic low level  
Note 2:Default advertisement on enable of Auto-Negotiation via the ANAR set to 100BASE-X Full-Duplex, 100BASE-X Half-Duplex, 10BASE-T Full-Duplex,  
and 10BASE-T Half-Duplex)  
Version A  
National Semiconductor  
37  
 复制成功!