DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
8.20 Universal Serial Bus (USB2.0)
The device includes two USB2.0 modules which support the Universal Serial Bus Specification Revision
2.0. The following are some of the major USB features that are supported:
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USB 2.0 peripheral at high speed (HS: 480 Mbps) and full speed (FS: 12 Mbps)
USB 2.0 host at HS, FS, and low speed (LS: 1.5 Mbps)
Each endpoint (other than endpoint 0, control only) can support all transfer modes (control, bulk,
interrupt, and isochronous)
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Supports high-bandwidth ISO mode
Supports 15 Transmit (TX) and 15 Receive (RX) endpoints including endpoint 0
FIFO RAM
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32K endpoint
Programmable size
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Includes two integrated PHYs
RNDIS-like mode for terminating RNDIS-type protocols without using short-packet termination for
support of MSC applications.
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USB Dual Role Device: Host Negotiation Protocol (HNP)
The USB2.0 peripherals do not support the following features:
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On-chip charge pump (VBUS Power must be generated external to the device.)
RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes
Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64, –
and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined
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USB OTG extension: Session Request Protocol (SRP)
For more detailed information on the USB2.0 peripheral, see the Universal Serial Bus (USB) chapter in the
device-specific Technical Reference Manual.
8.20.1 USB2.0 Peripheral Register Descriptions
The USB peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
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