DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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PHA=0
EPOL=1
SPI_SCS[x] (In)
1
1
3
3
8
2
2
9
POL=0
POL=1
SPI_SCLK (In)
SPI_SCLK (In)
SPI_D[x] (In)
4
4
5
5
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_SCS[x] (In)
SPI_SCLK (In)
1
3
2
8
2
3
9
POL=0
POL=1
1
SPI_SCLK (In)
SPI_D[x] (In)
4
4
5
5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 8-92. SPI Slave Mode Receive Timing
266
Peripheral Information and Timings
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