DM385, DM388
www.ti.com
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 8-80. Timing Requirements for SPI - Slave Mode (continued)
(see Figure 8-91 and Figure 8-92)
OPP100/OPP120/Turbo/Nitr
o
NO.
UNIT
MIN
12.92
12.92
MAX
8
9
tsu(SCS-SPICLK)
th(SPICLK-SCS)
Setup time, SPI_SCS[x] valid before SPI_CLK first edge(1)
Hold time, SPI_SCS[x] valid after SPI_CLK last edge(1)
ns
ns
PHA=0
EPOL=1
SPI_SCS[x] (In)
SPI_SCLK (In)
1
3
8
2
2
9
POL=0
POL=1
1
3
SPI_SCLK (In)
SPI_D[x] (Out)
6
7
6
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_SCS[x] (In)
SPI_SCLK (In)
1
1
3
2
8
2
3
9
POL=0
POL=1
SPI_SCLK (In)
SPI_D[x] (Out)
6
6
6
6
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 8-91. SPI Slave Mode Transmit Timing
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
265
Submit Documentation Feedback
Product Folder Links: DM385 DM388
TI [ TEXAS INSTRUMENTS ]
