DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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8.15 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)
The device includes 3 MMC/SD/SDIO Controllers which are compliant with MMC V4.3, Secure Digital Part
1 Physical Layer Specification V2.00 and Secure Digital Input Output (SDIO) V2.00 specifications.
The device MMC/SD/SDIO Controller has the following features:
•
•
•
•
•
•
•
•
•
MultiMedia card (MMC)
Secure Digital (SD) memory card
MMC/SD protocol support
SDIO protocol support
Programmable clock frequency
1024 byte read/write FIFO to lower system overhead
Slave EDMA transfer capability
SD High capacity support
SDXC card support
–
–
Supports only SDHC clock rates
Booting from SDXC cards is not supported
8.15.1 MMC/SD/SDIO Peripheral Register Descriptions
The MMC/SD/SDIO peripheral registers are described in the device-specific Technical Reference Manual.
Each register is documented as an offset from a base address for the peripheral. The base addresses for
all of the peripherals are in the device memory map (see Section 2.10).
8.15.2 MMC/SD/SDIO Electrical Data/Timing
Table 8-74. Timing Requirements for MMC/SD/SDIO
(see Figure 8-86, Figure 8-88)
OPP100/OPP120/
Turbo/Nitro
NO
.
UNIT
ALL MODES
MIN
4.1
1.9
4.1
1.9
MAX
1
2
3
4
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, SD_CMD valid before SD_CLK rising clock edge
Hold time, SD_CMD valid after SD_CLK rising clock edge
Setup time, SD_DATx valid before SD_CLK rising clock edge
Hold time, SD_DATx valid after SD_CLK rising clock edge
ns
ns
ns
ns
Table 8-75. Switching Characteristics Over Recommended Operating Conditions for MMC/SD/SDIO
(see Figure 8-85 through Figure 8-88)
OPP100/OPP120/
Turbo/Nitro
MODES
NO.
PARAMETER
UNIT
3.3 V STD
1.8 V SDR12
3.3 V HS
1.8 V SDR25
MIN
MAX
MIN
MAX
fop(CLK)
tc(CLK)
Operating frequency, SD_CLK
Operating period: SD_CLK
24
48 MHz
7
41.7
20.8
ns
fop(CLKID)
tc(CLKID)
tw(CLKL)
Identification mode frequency, SD_CLK
Identification mode period: SD_CLK
Pulse duration, SD_CLK low
400
400 kHz
8
9
2500.0
0.5*P(1)
0.5*P(1)
2500.0
0.5*P(1)
0.5*P(1)
ns
ns
ns
10 tw(CLKH)
Pulse duration, SD_CLK high
(1) P = SD_CLK period.
256
Peripheral Information and Timings
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