DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Table 8-73. Switching Characteristics Over Recommended Operating Conditions for McASP(1)
(see Figure 8-84)
OPP100/OPP120/
Turbo/Nitro
NO.
PARAMETER
UNIT
MIN
MAX
9
tc(AHCLKRX)
Cycle time, MCA[X]_AHCLKR/X
20(2)
ns
ns
ns
ns
0.5P -
2.5(3)
10 tw(AHCLKRX)
11 tc(ACLKRX)
12 tw(ACLKRX)
Pulse duration, MCA[X]_AHCLKR/X high or low
Cycle time, MCA[X]_ACLKR/X
20
0.5P -
2.5(3)
Pulse duration, MCA[X]_ACLKR/X high or low
ACLKR/X int
-2
1
5
Delay time, MCA[X]_ACLKR/X transmit edge to
MCA[X]_AFSR/X output valid
ACLKR/X ext in
11.5
13 td(ACLKRX-AFSRX)
ns
ns
Delay time, MCA[X]_ACLKR/X transmit edge to
MCA[X]_AFSR/X output valid with Pad Loopback
ACLKR/X ext out
1
11.5
ACLKX int
-2
1
5
Delay time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output valid
ACLKX ext in
11.5
14 td(ACLKX-AXR)
Delay time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output valid with Pad Loopback
ACLKX ext out
1
11.5
ACLKX int
-2
1
5
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance
ACLKX ext in
11.5
15 tdis(ACLKX-AXR)
ns
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance with Pad
Loopback
ACLKX ext out
1
11.5
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) 50 MHz
(3) P = AHCLKR/X period.
254
Peripheral Information and Timings
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