DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
www.ti.com
8.14.3 McASP (McASP[1:0]) Electrical Data/Timing
Table 8-72. Timing Requirements for McASP(1)
(see Figure 8-83)
OPP100/OPP120/
Turbo/Nitro
NO.
UNIT
MIN
MAX
1
2
3
4
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
Cycle time, MCA[x]_AHCLKR/X
20
ns
ns
ns
ns
0.5P -
2.5(2)
Pulse duration, MCA[x]_AHCLKR/X high or low
Cycle time, MCA[x]_ACLKR/X
20
0.5R -
2.5(3)
Pulse duration, MCA[x]_ACLKR/X high or low
ACLKR/X int
10.5
4
Setup time, MCA[x]_AFSR/X input valid before
MCA[X]_ACLKR/X
5
6
7
8
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
ns
ns
ns
ns
4
-1
1
Hold time, MCA[x]_AFSR/X input valid after
MCA[X]_ACLKR/X
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
1
10.5
4
Setup time, MCA[x]_AXR input valid before
MCA[X]_ACLKR/X
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
4
-1
1
Hold time, MCA[x]_AXR input valid after
MCA[X]_ACLKR/X
ACLKR/X ext in
ACLKR/X ext out
1
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = MCA[x]_AHCLKR/X period in nano seconds (ns).
(3) R = MCA[x]_ACLKR/X period in ns.
252
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DM385 DM388
TI [ TEXAS INSTRUMENTS ]
