DM385, DM388
www.ti.com
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
DVDD_DDR[0]
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
Figure 8-62. CK Routing for Four Single-Side DDR3 Devices
Rtt
A2
A3
A4
A3
AT
Vtt
=
Figure 8-63. ADDR_CTRL Routing for Four Single-Side DDR3 Devices
To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of
increased routing and assembly complexity. Figure 8-64 and Figure 8-65 show the routing for CK and
ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
239
Submit Documentation Feedback
Product Folder Links: DM385 DM388