DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 8-20. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps(1)
(see Figure 8-16)
OPP100/OPP120/
Turbo/Nitro
NO.
UNIT
MIN
MAX
tsu(RGRXD-
RGRXCH)
Setup time, receive selected signals valid before
EMAC[x]_RGRXC (at device) high/low
Internal delay
enabled
5
6
1.0
ns
ns
th(RGRXCH-
RGRXD)
Hold time, receive selected signals valid after
EMAC[x]_RGRXC (at device) high/low
Internal delay
enabled
1.0
(1) For RGMII, receive selected signals include: EMAC[x]_RGRXD[3:0] and EMAC[x]_RGRXCTL.
1
4
2
4
3
EMAC[x]_RGRXC
(at device)(A)
5
1st Half-byte
2nd Half-byte
6
EMAC[x]_RGRXD[3:0](B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
EMAC[x]_RGRXCTL(B)
RXERR
A. EMAC[x]_RGRXC must be externally delayed relative to the data and control pins. The internal delay can be enabled
or disabled via the EMAC RGMIIn_ID_MODE register.
B. Data and control information is received using both edges of the clocks. EMAC[x]_RGRXD[3:0] carries data bits 3-0
on the rising edge of EMAC[x]_RGRXC and data bits 7-4 on the falling edge of EMAC[x]_RGRXC. Similarly,
EMAC[x]_RGRXCTL carries RXDV on rising edge of EMAC[x]_RGRXC and RXERR on falling edge of
EMAC[x]_RGRXC.
Figure 8-16. EMAC Receive Interface Timing [RGMII Operation]
Table 8-21. Switching Characteristics Over Recommended Operating Conditions for RGTXC - RGMII
Operation for 10/100/1000 Mbit/s
(see Figure 8-17)
OPP100/OPP120/
Turbo/Nitro
NO.
UNIT
MIN
MAX
10 Mbps
360
36
440
44
1
tc(RGTXC)
tw(RGTXCH)
tw(RGTXCL)
tt(RGTXC)
Cycle time, EMAC[x]_RGTXC
100 Mbps
1000 Mbps
10 Mbps
ns
7.2
8.8
0.40*tc(RGTXC)
0.40*tc(RGTXC)
0.45*tc(RGTXC)
0.40*tc(RGTXC)
0.40*tc(RGTXC)
0.45*tc(RGTXC)
0.60*tc(RGTXC)
0.60*tc(RGTXC)
0.55*tc(RGTXC)
0.60*tc(RGTXC)
0.60*tc(RGTXC)
0.55*tc(RGTXC)
0.75
2
3
4
Pulse duration, EMAC[x]_RGTXC high
Pulse duration, EMAC[x]_RGTXC low
Transition time, EMAC[x]_RGTXC
100 Mbps
1000 Mbps
10 Mbps
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
0.75
0.75
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
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