DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Table 8-22. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII
Transmit(1)
(see Figure 8-17)
OPP100/OPP120
/
NO.
PARAMETER
UNIT
Turbo/Nitro
MIN
MAX
tsu(RGTXD-
RGTXCH)
th(RGTXCH-
RGTXD)
Setup time, transmit selected signals valid before
EMAC[x]_RGTXC (at device) high/low
5
6
Internal delay enabled
Internal delay enabled
1.2
ns
ns
Hold time, transmit selected signals valid after
EMAC[x]_RGTXC (at device) high/low
1.2
(1) For RGMII, transmit selected signals include: EMAC[x]_RGTXD[3:0] and EMAC[x]_RGTXCTL.
RGTXC at device pins
Internal RGTXC
1
4
2
4
3
EMQAC[x]_RGTXC
(at device)(A)
1
5
EMAC[x]_RGTXD[3:0](B)
EMAC[x]_RGTXCTL(B)
1st Half-byte
2nd Half-byte
TXERR
6
2
TXEN
A. RGTXC is delayed internally before being driven to the EMAC[x]_RGTXC pin. The internal delay can be enabled or
disabled via the EMAC RGMIIn_ID_MODE register.
B. Data and control information is transmitted using both edges of the clocks. EMAC[x]_RGTXD[3:0] carries data bits 3-0
on the rising edge of EMAC[x]_RGTXC and data bits 7-4 on the falling edge of EMAC[x]_RGTXC. Similarly,
EMAC[x]_RGTXCTL carries TXEN on rising edge of EMAC[x]_RGTXC and TXERR of falling edge of
EMAC[x]_RGTXC.
Figure 8-17. EMAC Transmit Interface Timing [RGMII Operation]
178
Peripheral Information and Timings
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