DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
8.6.2 EMAC Electrical Data/Timing
8.6.2.1 EMAC MII and GMII Electrical Data/Timing
GMII mode is not supported for OPP50.
Table 8-11. Timing Requirements for EMAC[x]_MRCLK - [G]MII Operation
(see Figure 8-9)
OPP100/OPP120/Turbo/Nitro
1000 Mbps (1 Gbps)
(GMII Only)
100 Mbps
10 Mbps
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1
2
tc(MRCLK)
Cycle time, EMAC[x]_MRCLK
8
40
400
ns
ns
Pulse duration,
EMAC[x]_MRCLK high
tw(MRCLKH)
2.8
2.8
14
14
140
140
Pulse duration,
EMAC[x]_MRCLK low
3
4
tw(MRCLKL)
tt(MRCLK)
ns
ns
Transition time,
EMAC[x]_MRCLK
1
3
3
1
4
2
3
EMAC[x]_MRCLK
4
Figure 8-9. EMAC[x]_MRCLK Timing (EMAC Receive) - [G]MII Operation
Table 8-12. Timing Requirements for EMAC[x]_MTCLK - [G]MII Operation
(see Figure 8-14)
OPP100/OPP120/Turbo/Nitro
1000 Mbps (1 Gbps)
(GMII Only)
100 Mbps
10 Mbps
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1
2
tc(MTCLK)
Cycle time, EMAC[x]_MTCLK
8
40
400
ns
ns
Pulse duration,
EMAC[x]_MTCLK high
tw(MTCLKH)
2.8
2.8
14
14
140
140
Pulse duration,
EMAC[x]_MTCLK low
3
4
tw(MTCLKL)
tt(MTCLK)
ns
ns
Transition time,
EMAC[x]_MTCLK
1
3
3
1
4
2
3
EMAC[x]_MTCLK
4
Figure 8-10. EMAC[x]_MTCLK Timing (EMAC Transmit) - [G]MII Operation
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
173
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