DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
www.ti.com
Table 7-15. Timing Requirements for AUX_MXI/AUX_CLKIN (1) (2) (see Figure 7-14)
OPP100
NOM
50
NO.
UNIT
MAX
MIN
33.3
1
2
3
4
5
6
tc(AMXI)
tw(AMXIH)
tw(AMXIL)
tt(AMXI)
tJ(AMXI)
Sf
Cycle time, AUXOSC_MXI/AUX_CLKIN
50 ns
0.55C ns
0.55C ns
Pulse duration, AUXOSC_MXI/AUX_CLKIN high
Pulse duration, AUXOSC_MXI/AUX_CLKIN low
Transition time, AUXOSC_MXI/AUX_CLKIN
Period jitter, AUXOSC_MXI/AUX_CLKIN
0.45C
0.45C
7
ns
0.02C ns
± 50 ppm
Frequency stability, AUXOSC_MXI/AUX_CLKIN(3)
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = AUX_CLKIN cycle time in ns. For example, when AUXOSC_MXI/AUX_CLKIN frequency is 20 MHz, use C = 50 ns.
(3) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC.
5
1
4
1
2
AUXOSC_MXI/
AUX_CLKIN
3
4
Figure 7-14. AUX_MXI/AUX_CLKIN Timing
152
Power, Reset, Clocking, and Interrupts
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DM385 DM388
TI [ TEXAS INSTRUMENTS ]
