DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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2.5 Media Controller Overview
The Media Controller has the responsibility of managing the HDVPSS, HDVICP2, and ISS modules.
2.6 HDVICP2 Overview
The HDVICP2 is a Video Encoder/Decoder hardware accelerator supporting a range of encode, decode,
and transcode operations for most major video codec standards. The main video Codec standards
supported in hardware are MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP, RV9/10, AVS-1.0,
and ON2 VP6.2/VP7.
Supports up to 4K x 2K @ 15fps, 12Mpixels @ 10fps, 20Mpixels @ 6fps, and so on.
The HDVICP2 hardware accelerator is composed of the following elements:
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Motion estimation acceleration engine
Loop filter acceleration engine
Sequencer, including its memories and an interrupt controller
Intra-prediction estimation engine
Calculation engine
Motion compensation engine
Entropy coder/decoder
Video Direct Memory Access (DMA)
Synchronization boxes
Shared L2 controller
Local interconnect
2.7 Face Detect (FD) Overview
The device Face Detection (FD) module performs face detection and tracking within a picture stored in
memory. This module is typically used for video encoding, face-based priority auto-focusing, or red-eye
removal. The FD module supports QVGA resolution inputs stored in DRR memory in 8-bit Luma format. In
addition, it uses 51.25KB of DDR for its working memory.
The FD module supports the following features:
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Input image:
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QVGA Input Image Size (H x V = 320 x 240)
8-bit Gray Scale Data (0x00 = Black and 0xFF = White)
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Device Overview
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