DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
2.10 Memory Map Summary
The device has multiple on-chip memories associated with its processor and subsystems. To help simplify
software development a unified memory map is used where possible to maintain a consistent view of
device resources across all bus masters.
2.10.1 L3 Memory Map
Table 2-3 shows the L3 memory map for all system masters (including Cortex-A8).
For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see
Section 5.
Table 2-3. L3 Memory Map
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
DESCRIPTION
Reserved (BOOTROM)
0x0000_0000
0x1000_0000
0x00FF_FFFF
0x1FFF_FFFF
16MB
496MB
General Purpose Memory Controller (GPMC)
External Memory Space
0x2000_0000
0x3000_0000
0x4000_0000
0x2FFF_FFFF
0x3FFF_FFFF
0x4001_FFFF
256MB
256MB
128KB
PCIe
Reserved
Reserved
ARM Cortex-A8 ROM
(Accessible by ARM Cortex-A8 only)
0x4002_0000
0x4002_BFFF
48KB
0x4002_C000
0x402F_0000
0x402E_FFFF
0x402F_03FF
2832KB
1KB
Reserved
Reserved
ARM Cortex-A8 RAM
(Accessible by ARM Cortex-A8 only)
0x402F_0400
0x402F_FFFF
64KB - 1KB
0x4030_0000
0x4034_0000
0x4080_0000
0x4084_0000
0x40E0_0000
0x40E0_8000
0x40F0_0000
0x40F0_8000
0x4100_0000
0x4200_0000
0x4400_0000
0x4440_0000
0x4480_0000
0x44C0_0000
0x4600_0000
0x4640_0000
0x4680_0000
0x46C0_0000
0x4700_0000
0x4740_0000
0x4780_0000
0x4781_0000
0x4781_2000
0x47C0_0000
0x47C0_0000
0x4033_FFFF
0x407F_FFFF
0x4083_FFFF
0x40DF_FFFF
0x40E0_7FFF
0x40EF_FFFF
0x40F0_7FFF
0x40FF_FFFF
0x41FF_FFFF
0x43FF_FFFF
0x443F_FFFF
0x447F_FFFF
0x44BF_FFFF
0x45FF_FFFF
0x463F_FFFF
0x467F_FFFF
0x46BF_FFFF
0x46FF_FFFF
0x473F_FFFF
0x477F_FFFF
0x4780_FFFF
0x4781_1FFF
0x47BF_FFFF
0x47FF FFFF
0x47C0_BFFF
256KB
4864KB
256KB
5888KB
32KB
992KB
32KB
992KB
16MB
32MB
4MB
OCMC SRAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
L3 Fast configuration registers
4MB
L3 Mid configuration registers
4MB
L3 Slow configuration registers
20MB
4MB
Reserved
McASP0 Data Peripheral Registers
4MB
McASP1 Data Peripheral Registers
4MB
Reserved
4MB
HDMI
4MB
Reserved
4MB
USB
64KB
8KB
Reserved
MMC/SD/SDIO2 Peripheral Registers
4MB - 72KB
4MB
Reserved
Reserved
Reserved
48KB
Copyright © 2013, Texas Instruments Incorporated
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