DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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2.3 Device Compatibility
2.4 ARM® Cortex™-A8 Microprocessor Unit (Processor) Subsystem Overview
The ARM® Cortex™-A8 Subsystem is designed to allow the ARM Cortex-A8 master control of the device.
In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystems,
peripherals, and external memories.
The ARM Cortex-A8 Subsystem includes the following features:
•
ARM Cortex-A8 RISC processor:
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–
–
–
–
–
–
ARMv7 ISA plus Thumb2™, JazelleX™, and Media Extensions
NEON™ Floating-Point Unit
Enhanced Memory Management Unit (MMU)
Little Endian
32KB L1 Instruction Cache
32KB L1 Data Cache
256KB L2 Cache with Error Correction Code (ECC)
•
•
•
•
•
CoreSight Embedded Trace Module (ETM)
ARM Cortex-A8 Interrupt Controller (AINTC)
Embedded PLL Controller (PLL_ARM)
64KB Internal RAM
48KB Internal Public ROM
Figure 2-1 shows the ARM Cortex-A8 Subsystem for the device.
System Events
128
L3
DMM
DEVOSC
PLL_ARM
128
128 128
128
32
128
128
ARM Cortex-A8
Interrupt Controller
(AINTC)
ARM Cortex-A8
32
64
32KB L1I$ 32KB L1D$
256KB L2$
48KB ROM
64KB RAM
Arbiter
ETM
NEON
Trace
64
Debug
ICECrusher
Figure 2-1. ARM Cortex-A8 Subsystem
2.4.1 ARM Cortex-A8 RISC Processor
The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose microprocessors.
This processor is targeted at multi-tasking applications where full memory management, high
performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the
ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM
Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem,
including:
•
•
•
•
•
ARM Cortex-A8 Integer Core
Superscalar ARMv7 Instruction Set
Thumb-2 Instruction Set
Jazelle RCT Acceleration
CP14 Debug Coprocessor
10
Device Overview
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