DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
www.ti.com
Table 2-3. L3 Memory Map (continued)
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
DESCRIPTION
0x47C0_C000
0x47C0_C400
0x47C0_C800
0x47C0_CC00
0x47C0_D000
0x4800_0000
0x47C0_C3FF
0x47C0_C7FF
0x47C0_CBFF
0x47C0_CFFF
0x47FF FFFF
0x48FF_FFFF
1KB
1KB
Reserved
DDR PHY Registers
Reserved
1KB
1KB
Reserved
4052KB
16MB
Reserved
L4 Slow Peripheral Domain
(see Table 2-5)
0x4900_0000
0x4910_0000
0x4980_0000
0x4990_0000
0x49A0_0000
0x49B0_0000
0x49C0_0000
0x4A00_0000
0x490F_FFFF
0x497F_FFFF
0x498F_FFFF
0x499F_FFFF
0x49AF_FFFF
0x49BF_FFFF
0x49FF_FFFF
0x4AFF_FFFF
1MB
7MB
1MB
1MB
1MB
1MB
4MB
16MB
EDMA TPCC Registers
Reserved
EDMA TPTC0 Registers
EDMA TPTC1 Registers
EDMA TPTC2 Registers
EDMA TPTC3 Registers
Reserved
L4 Fast Peripheral Domain
(see Table 2-4)
0x4B00_0000
0x4C00_0000
0x4D00_0000
0x4E00_0000
0x5000_0000
0x5100_0000
0x5200_0000
0x5500_0000
0x5600_0000
0x5700_0000
0x5800_0000
0x5900_0000
0x5A00_0000
0x5C00_0000
0x5E00_0000
0x6000_0000
0x8000_0000
0x1 0000 0000
0x4BFF_FFFF
0x4CFF_FFFF
0x4DFF_FFFF
0x4FFF_FFFF
0x50FF_FFFF
0x51FF_FFFF
0x54FF_FFFF
0x55FF_FFFF
0x56FF_FFFF
0x57FF_FFFF
0x58FF_FFFF
0x59FF_FFFF
0x5BFF_FFFF
0x5DFF_FFFF
0x5FFF_FFFF
0x7FFF_FFFF
0xFFFF_FFFF
0x1 FFFF FFFF
16MB
16MB
16MB
32MB
16MB
16MB
48MB
16MB
16MB
16MB
16MB
16MB
32MB
32MB
32MB
512MB
2GB
Emulation Subsystem
DDR Registers
Reserved
DDR DMM Registers
GPMC Registers
PCIE Registers
Reserved
Media Controller
Reserved
Reserved
HDVICP2 Configuration
HDVICP2 SL2
Reserved
ISS
Reserved
DDR DMM Tiler Window (see Table 2-6)
DDR
4GB
DDR DMM Tiler Extended Address Map
(ISS and HDVPSS only) [see Table 2-6]
16
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