DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 2-2. Characteristics of the Processor (continued)
HARDWARE FEATURES
DM385/DM388
1 (1-bit or 4-bit or 8-bit modes)
and
MMC/SD/SDIO
1 (8-bit mode) or
2 (1-bit or 4-bit modes)
I2C
4 Master or Slave
Media Controller
Controls HDVPSS, HDVICP2, and ISS
2 (6/2 Serializers, each with
Transmit/Receive and DIT capability)
McASP
RTC
1
GPIO
Up to 125 pins
Spinlock Module
Mailbox Module
Size (Bytes)
1 (up to 128 H/W Semaphores)
1 (with 12 Mailboxes)
640KB RAM, 48KB ROM
ARM
32KB I-cache
32KB D-cache
256KB L2 Cache with ECC
64KB RAM
On-Chip Memory
JTAG BSDL ID
Organization
48KB Boot ROM
ADDITIONAL SHARED MEMORY
256KB On-chip RAM
see Section 8.5.3.1, JTAG ID (JTAGID)
Register Description
DEVICE_ID Register (address location: 0x4814 0600)
CPU Frequency
Cycle Time
MHz
ns
ARM® Cortex™-A8 up to 1000 MHz
ARM® Cortex™ -A8 1.0 ns
DEEP SLEEP,
Core Logic (V)
OPP100, OPP120,
Turbo, Nitro
0.83 V – 1.35 V
Voltage
I/O (V)
16 x 16 mm
μm
1.35 V, 1.5 V, 1.8 V, 3.3 V
609-Pin BGA (AAR) [with Via Channel™
Technology]
Package
Process Technology
0.045 μm
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status
PD
Copyright © 2013, Texas Instruments Incorporated
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