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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
5.7 Inter-Integrated Circuit (I2C)
For more information, see the Inter-Integrated Circuit (I2C) section of the AM335x ARM Cortex-A8
Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).
5.7.1 I2C Electrical Data and Timing
Table 5-68. I2C Timing Conditions - Slave Mode
STANDARD MODE
MIN MAX
FAST MODE
MIN
TIMING CONDITION PARAMETER
UNIT
MAX
Output Condition
Cb
Capacitive load for each bus line
400
400
pF
Table 5-69. Timing Requirements for I2C Input Timings
(see Figure 5-68)
STANDARD MODE
FAST MODE
NO.
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
us
us
Setup Time, SCL high before SDA low (for a repeated
START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
3
th(SDAL-SCLL)
us
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(1)
0(2)
us
us
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(2)
3.45(3)
0.9(3) us
Pulse duration, SDA high between STOP and START
conditions
8
9
tw(SDAH)
tr(SDA)
4.7
1.3
us
Rise time, SDA
1000
1000
300
300 ns
300 ns
300 ns
300 ns
us
10 tr(SCL)
Rise time, SCL
11 tf(SDA)
Fall time, SDA
12 tf(SCL)
Fall time, SCL
300
13 tsu(SCLH-SDAH)
14 tw(SP)
Setup time, high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
4
0
0.6
0
50
50 ns
(1) A fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the
standard-mode I2C-Bus Specification) before the SCL line is released.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
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