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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
AM335x
DQS[x]
DDR3
DQS[x]+
DQS[x]-
DQS[x]
IO Buffer
IO Buffer
Routed Differentially
x = 0, 1
Figure 5-62. DQS[x] Topology
AM335x
DQ[x]
DDR3
DQ[x]
DQ[x]
IO Buffer
IO Buffer
x = 0, 1
Figure 5-63. DQ[x] Topology
5.6.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
Figure 5-64 and Figure 5-65 show the DQS[x] and DQ[x] routing.
DQS[x]
DQS[x]+
DQS[x]-
Routed Differentially
x = 0, 1
Figure 5-64. DQS[x] Routing With Any Number of Allowed DDR3 Devices
DQ[x]
x = 0, 1
Figure 5-65. DQ[x] Routing With Any Number of Allowed DDR3 Devices
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