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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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DQLMX0
DQ0
DQ[0:7], DM0, DQS0
DQ[8:15], DM1, DQS1
DQ1
DQLMX1
DQLMY0
DQLMY1
1
0
DQ0 - DQ1 represent data bytes 0 - 1.
There are two DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the byte;
therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
Figure 5-67. DQLM for Any Number of Allowed DDR3 Devices
Table 5-67. DQS[x] and DQ[x] Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
DQLM0
DQLM1
25
UNIT
mils
mils
mils
mils
mils
DQ0 nominal length(3)(4)
DQ1 nominal length(3)(5)
DQ[x] skew(6)
2
3
4
DQS[x] skew
DQS[x]-to-DQ[x] skew(6)(7)
5
5
25
6
Center-to-center DQ[x] to other DDR3 trace spacing(8)(9)
Center-to-center DQ[x] to other DQ[x] trace spacing(8)(10)
DQS[x] center-to-center spacing(11)
4w
3w
7
8
9
DQS[x] center-to-center spacing to other net(8)
4w
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) DQLMn is the longest Manhattan distance of a byte. For definition, see Section 5.6.2.3.6.2 and Figure 5-67.
(4) DQLM0 is the longest Manhattan length for the DQ0 net class.
(5) DQLM1 is the longest Manhattan length for the DQ1 net class.
(6) Length matching is only done within a byte. Length matching across bytes is not required.
(7) Each DQS clock net class is length matched to its associated DQ signal net class.
(8) Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.
(9) Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class.
(10) This applies to spacing within same DQ[x] signal net class.
(11) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-
ended impedance defined in Table 5-60.
188
Peripheral Information and Timings
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