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AM3352BZCZD80 参数 Datasheet PDF下载

AM3352BZCZD80图片预览
型号: AM3352BZCZD80
PDF下载: 下载PDF文件 查看货源
内容描述: 的Sitara AM335x ARM Cortex-A8的微处理器(MPU ) [Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs)]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 236 页 / 2887 K
品牌: TI [ TEXAS INSTRUMENTS ]
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AM3359, AM3358, AM3357  
AM3356, AM3354, AM3352  
SPRS717F OCTOBER 2011REVISED APRIL 2013  
www.ti.com  
5.6.2.3.3.4 Placement  
Figure 5-50 shows the required placement for the AM335x device as well as the DDR3 devices. The  
dimensions for this figure are defined in Table 5-61. The placement does not restrict the side of the PCB  
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace  
lengths and allow for proper routing space.  
X1  
X2  
DDR3  
Interface  
Y
Figure 5-50. Placement Specifications  
Table 5-61. Placement Specifications(1)  
NO.  
1
PARAMETER  
MIN  
MAX  
1000  
600  
UNIT  
mils  
mils  
mils  
w
X1(2)(3)(4)  
X2(2)(3)  
Y Offset(2)(3)(4)  
2
3
1500  
4
Clearance from non-DDR3 signal to DDR3 keepout region(5)(6)  
4
(1) DDR3 keepout region to encompass entire DDR3 routing area.  
(2) For dimension definitions, see Figure 5-50.  
(3) Measurements from center of AM335x device to center of DDR3 device.  
(4) Minimizing X1 and Y improves timing margins.  
(5) w is defined as the signal trace width.  
(6) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.  
176  
Peripheral Information and Timings  
Copyright © 2011–2013, Texas Instruments Incorporated  
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352  
 
 
 
 
 
 
 
 
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