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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Table 5-55. DQS[x] and DQ[x] Routing Specification(1)
PARAMETER
MIN
TYP
MAX
2w
UNIT
1
2
3
4
5
6
7
8
Center-to-center DQS[x] spacing
DQS[x] differential pair skew length mismatch(2)
Center-to-center DDR_DQS[x] to other DDR2 trace spacing(3)
DQS[x] and DQ[x] nominal trace length(4)
DQ[x]-to-DQS[x] skew length mismatch(4)
DQ[x]-to-DQ[x] skew length mismatch(4)
25
mils
4w
DQLM-50
DQLM
DQLM+50
100
mils
mils
mils
100
Center-to-center DQ[x] to other DDR2 trace spacing(3)(5)
Center-to-center DQ[x] to other DQ[x] trace spacing(3)(6)
4w
3w
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 5-46.
(3) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) There is no requirement for skew matching between data bytes; that is, from net classes DQS0 and DQ0 to net classes DQS1 and DQ1.
(5) Signals from one DQ net class should be considered other DDR2 traces to another DQ net class.
(6) DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.
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